Flash memory device and method of programming the same

ABSTRACT

A flash memory device includes a first memory cell, a second memory cell, a row decoder, and a bias generator. The first memory cell is a selected memory cell, and the second memory cell is an unselected memory cell connected with a bit line that is connected to the first memory cell. The row decoder controls a word line voltage to be applied to the first memory cell and controls an unselected source line voltage to be applied to the second memory cell. The bias generator generates the word line voltage based on a threshold voltage of a word line transistor changing with an ambient temperature and generates the unselected source line voltage based on a voltage level of the selected bit line.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority from Korean Patent Application No.10-2017-0135441, filed Oct. 18, 2017, in the Korean IntellectualProperty Office, the disclosures of which are incorporated by referenceherein in their entireties.

BACKGROUND 1. Field

Devices and methods consistent with exemplary embodiments relate to asemiconductor memory device, and more particularly, relate to a flashmemory device and a method of programming the same.

2. Description of the Related Art

A semiconductor memory refers to a memory device that is implementedusing semiconductor such as silicon (Si), germanium (Ge), galliumarsenide (GaAs), indium phospide (InP), or the like. The semiconductormemory device is classified as a volatile memory device, such as adynamic random access memory (DRAM), a static RAM (SRAM), or the like,or a nonvolatile memory device, such as an electrically erasable andprogrammable ROM (EEPROM), a flash memory device, a phase-change RAM(PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectricRAM (FRAM), or the like.

A nonvolatile memory may retain data stored therein even at power-off.In particular, a flash memory has advantages such as high program speed,low power consumption, storing of a large amount of data, and the like.Among the nonvolatile memory devices, the flash memory device that usesa floating gate way to store bit information through injection ofcharges into a floating gate formed of polysilicon is being variouslyused to implement a storage medium.

Characteristics of memory cells included in the flash memory device mayvary depending on an ambient temperature. The change in characteristicsof the memory cells has an influence on injection of charges into afloating gate, thus having an influence on a program characteristic ofthe flash memory device. Accordingly, there is a need to prevent aprogram characteristic of the flash memory device from deterioratingdepending on a temperature.

SUMMARY

One or more exemplary embodiments provide a flash memory device thatprevents deterioration of a program characteristic due to a temperaturechange in a program operation and minimizes a leakage current of anunselected memory cell and a method of programming the same.

According to an exemplary embodiment, a flash memory device includes afirst memory cell, a second memory cell, a row decoder, and a biasgenerator. The first memory cell includes a first cell transistor. Afirst terminal of a first transistor is connected to a selected bit linethrough a first word line transistor, and a second terminal thereof isconnected to a selected source line. The second memory cell includes asecond cell transistor. A first terminal of a second transistor isconnected to the selected bit line through a second word linetransistor, and a second terminal thereof is connected to an unselectedsource line.

The row decoder controls a word line voltage to be applied to a firstword line connected to a control terminal of the first word linetransistor. The row decoder controls a selected source line voltage tobe applied to the selected source line and an unselected source linevoltage to be applied to the unselected source line. The bias generatorgenerates the word line voltage based on a threshold voltage of thefirst word line transistor varying with an ambient temperature. The biasgenerator generates the unselected source line voltage based on avoltage level of the selected bit line.

According to an exemplary embodiment, a program method of a flash memorydevice programs a selected memory cell. The method includes detecting anambient temperature, generating a word line voltage based on thedetected ambient temperature, generating an unselected source linevoltage based on the word line voltage and a voltage level of theselected bit line, applying the word line voltage to the selected memorycell, and applying the unselected source line voltage to the unselectedmemory cell.

BRIEF DESCRIPTION OF THE FIGURES

The above and other aspects will become apparent by describing in detailexemplary embodiments thereof with reference to the accompanyingdrawings.

FIG. 1 is a block diagram of a flash memory device according to anexemplary embodiment.

FIG. 2 is an exemplary circuit diagram of a memory cell array of FIG. 1.

FIG. 3 is a sectional view of a memory cell of FIG. 2.

FIG. 4 is a circuit diagram for describing how a selected memory cell isprogrammed at a selected bit line.

FIG. 5 is a block diagram illustrating an exemplary configuration of abias generator of FIG. 1.

FIG. 6 is a view illustrating an exemplary configuration of atemperature detecting circuit of FIG. 5.

FIG. 7 is a graph for describing a change in a voltage according to atemperature in the temperature detecting circuit of FIG. 6.

FIG. 8 is a view illustrating an exemplary configuration of a word linevoltage generator of FIG. 5.

FIG. 9 is a view illustrating an exemplary configuration of anunselected source line voltage generator of FIG. 5.

FIG. 10 is a graph for describing a relationship between a word linevoltage, an unselected source line voltage, and a selected bit linevoltage generated by a bias generator of FIG. 5.

FIG. 11 is a flowchart of a program method of a flash memory deviceaccording to an exemplary embodiment.

FIG. 12 is an exemplary block diagram of a memory system including theflash memory device of FIG. 1.

DETAILED DESCRIPTION

Below, embodiments will be described clearly and in detail withreference to accompanying drawings to such an extent that an ordinaryone in the art implements embodiments of the invention.

FIG. 1 is a block diagram of a flash memory device according to anexemplary embodiment.

Referring to FIG. 1, a flash memory device 100 includes a memory cellarray 110, a row decoder 120, a bit line selection circuit 130, a datainput/output (I/O) circuit 140, a control circuit 150, and a biasgenerator 160.

The memory cell array 110 is connected to the row decoder 120 throughword lines WL and source lines SL. The memory cell array 110 isconnected to the bit line selection circuit 130 through bit lines BL.The memory cell array 110 includes a plurality of memory cells. Forexample, memory cells arranged in a row direction may share one wordline or source line, and memory cells arranged in a column direction mayshare one bit line. Each of the memory cells may be configured to storeone or more bits. The memory cell array 110 will be more fully describedlater.

The row decoder 120 is provided with a word line voltage and a sourceline voltage from the bias generator 160. The row decoder 120 may selecta word line in a program operation or a read operation. The row decoder120 may provide a word line voltage (or a program voltage) for theprogram operation to a selected word line. The row decoder 120 mayprovide a word line voltage (or a read voltage) for the read operationto a selected word line. The row decoder 120 may select a source line inthe program operation. The row decoder 120 may provide a selected sourceline voltage for the program operation to a selected source line. Therow decoder 120 may provide an unselected source line voltage to anunselected source line.

The row decoder 120 may be provided with a first voltage from a highvoltage generator 165 included in the bias generator 160. Alternatively,the row decoder 120 may be provided with a second voltage having avoltage level lower than the first voltage from a middle voltagegenerator 166 included in the bias generator 160. For example, the rowdecoder 120 may provide the second voltage to a selected source line inthe program operation. In the program operation, the row decoder 120 mayprovide the first voltage to a coupling gate of a memory cell to bedescribed later and may provide the second voltage of an erase gate ofthe memory cell to be described later. In an erase operation, the rowdecoder 120 may provide the first voltage to the erase gate.

The bit line selection circuit 130 may select a bit line in the programoperation or the read operation. In the program operation, a programcurrent may flow to a bit line selected by the bit line selectioncircuit 130. In the program operation, a suppression voltage may beapplied to a bit line that is not selected by the bit line selectioncircuit 130. In this case, memory cells connected to the unselected bitline may not be programmed. In the read operation, a read current mayflow to a bit line selected by the bit line selection circuit 130.

The data input/output circuit 140 is connected with the bit lineselection circuit 130. The data input/output circuit 140 may receiveprogram data DATA from the outside of the flash memory device 100 in theprogram operation. For example, the data input/output circuit 140 mayreceive program data from a memory controller (not illustrated). Thedata input/output circuit 140 may provide read data to the outside ofthe flash memory device 100, for example, the memory controller (notillustrated) in the read operation.

The control circuit 150 controls overall operations of the flash memorydevice 100. The control circuit 150 may control the program operation,the read operation, and/or the erase operation of the flash memorydevice 100 by using a command CMD and an address ADDR provided from thememory controller (not illustrated). For example, the control circuit150 may allow the row decoder 120 to select a word line and a sourceline based on the address ADDR. The control circuit 150 may allow therow decoder 120 to provide a word line voltage to a selected word lineand a selected source line voltage to a selected source line. Also, thecontrol circuit 150 may allow the bit line selection circuit 130 toselect a bit line connected to a memory cell corresponding to a targetof the program operation or the read operation. Also, the controlcircuit 150 may allow the data input/output circuit 140 to provide readdata or to receive program data.

The control circuit 150 may control the bias generator 160. The controlcircuit 150 may control a voltage output by the bias generator 160 tothe row decoder 120, depending on the program operation, the readoperation, and the erase operation. For example, in the programoperation, the control circuit 150 may allow the bias generator 160 todetermine a level of a word line voltage to be provided to a selectedword line, a level of a selected source line voltage to be provided to aselected source line, and a level of an unselected source line voltageto be provided to an unselected source line.

The bias generator 160 generates a voltage to be provided to the rowdecoder 120. The bias generator 160 may include the high voltagegenerator 165 and the middle voltage generator 166. However, thedisclosure may not be limited thereto. For example, the bias generator160 may further include voltage generators for generating voltages ofvarious levels. For example, the bias generator 160 may further includea word line voltage generator and an unselected source line voltagegenerator used in the program operation. The word line voltage generatorand the unselected source line voltage generator may generate voltages,the levels of which vary with an ambient temperature, which will bedescribed with reference to FIG. 5.

The high voltage generator 165 may generate the first voltage undercontrol of the control circuit 150 and may provide the first voltage tothe row decoder 120. The high voltage generator 165 may receive areference voltage Vref and may generate the first voltage higher inlevel than the reference voltage Vref. To this end, the bias generator160 may further include a high voltage oscillator (not illustrated). Thefirst voltage provided to the row decoder 120 may be applied to acoupling gate in the program operation.

The middle voltage generator 166 may generate the second voltage undercontrol of the control circuit 150 and may provide the second voltage tothe row decoder 120. The middle voltage generator 166 may receive thereference voltage Vref and may generate the second voltage higher inlevel than the reference voltage Vref and lower than the first voltage.Alternatively, the middle voltage generator 166 may divide a voltagegenerated in the high voltage generator 165 to generate the secondvoltage. The second voltage provided to the row decoder 120 may beapplied to a source line and an erase gate line selected in the programoperation.

FIG. 2 is an exemplary circuit diagram of a memory cell array of FIG. 1.

The memory cell array 110 of FIG. 2 is illustrated as including floatinggate memory cells of a split gate type. However, the disclosure may notbe limited thereto. Accordingly, the flash memory device 100 of FIG. 1may include a memory cell array that is different from the memory cellarray 110 of FIG. 2.

The memory cell array 110 may include a plurality of memory cells formedin a semiconductor substrate. It is assumed that the memory cell array110 includes m-by-n memory cells. Bit lines BL1, BL2, . . . BLn-1, andBLn, word lines WL1, WL2, . . . WLm-1, and WLm, coupling gate lines CG1,CG2, . . . CGm-1, and CGm, source lines SL1 to SLm/2, and erase gatelines EG1 to EGm/2 connected with the plurality of memory cells may beformed in the semiconductor substrate. The plurality of memory cells maybe connected to different word lines or to different bit lines. That is,the memory cell array 110 may be a memory cell array of a NOR flashtype.

The memory cell array 110 may include a first memory cell 111 and asecond memory cell 112. The first memory cell 111 includes a first wordline transistor Trw1 and a first cell transistor Trc1. The first memorycell 111 is connected with a first word line WL1, a first coupling gateline CG1, a first erase gate line EG1, a first source line SL1, and afirst bit line BL1.

The first word line transistor Trw1 includes a first terminal (or afirst end) connected to the first bit line BL1, a second terminal (or asecond end) connected to the first source line SL1 through the firstcell transistor Trc1, and a control terminal connected to the first wordline WL1. When a voltage provided to the first word line WL1 is greaterthan a threshold voltage of the first word line transistor Trw1, thefirst word line transistor Trw1 may form a channel area between thefirst terminal and the second terminal. The threshold voltage may bedetermined according to a characteristic of the first word linetransistor Trw1. The voltage provided to the first word line WL1 maydetermine a bit line voltage applied to the first bit line BL1. A levelof the bit line voltage applied to the first bit line BL1 may correspondto a difference between the voltage of the first word line WL1 and athreshold voltage of the first word line transistor Trw1.

The first cell transistor Trc1 includes a first terminal (or a firstend) connected to the first bit line BL1 through the first word linetransistor Trw1, a second terminal (or a second end) connected to thefirst source line SL1, and a control terminal connected to the firstcoupling gate line CG1. Also, the first cell transistor Trc1 may furtherinclude a floating gate into which charges are injected in a programoperation. In the program operation, hot carriers may be injected intothe floating gate of the first cell transistor Trc1 based on the voltageprovided to the first coupling gate line CG1. Below, it is assumed thatthe first memory cell 111 is a memory cell selected for the programoperation.

A potential difference between the voltage provided to the first sourceline SL1 and the voltage applied to the first bit line BL1 may generatehot carriers. To this end, a level of the voltage applied to the firstsource line SL1 may be higher than a level of the voltage applied to thefirst bit line BL1. A level of a voltage provided to the first erasegate line EG1 adjacent to the first source line SL1 may be the same as alevel of the voltage applied to the first source line SL1. The voltageprovided to the first coupling gate line CG1 generates a strong electricfield such that hot carriers are injected into the floating gate.Accordingly, a high voltage may be applied to the first coupling gateline CG1.

A program characteristic of the first memory cell 111 may be improved asa large amount of hot carriers are generated or as a large amount of hotcarriers are injected into the floating gate. In the case where a levelof a voltage applied to the first source line SL1 increases, a potentialdifference between a voltage provided to the first source line SL1 and avoltage applied to the first bit line BL1 may increase. This may meanthat the amount of hot carriers generated increases. Alternatively, inthe case where a level of a voltage applied to the first coupling gateline CG1 increases, the amount of hot carriers injected into thefloating gate may increase.

However, in the case of increasing a voltage to be applied to the firstsource line SL1 or the first coupling gate line CG1, the increasedvoltage may be applied to other memory cells connected to the firstsource line SL1 or the first coupling gate line CG1. That is, electronsmay be injected into a floating gate of another memory cell that is notselected or may be ejected from the floating gate of another memorycell. For example, in the case where a level of a voltage applied to thefirst source line SL1 increases, even if the second memory cell 112 thatshares the first source line SL1 with the first memory cell 11 or amemory cell adjacent to the first memory cell 111 in a row direction isunselected, the second memory cell 112 or the adjacent memory cell maybe programmed in the program operation.

In the case where a level of a voltage applied to the first bit line BL1decreases, a potential difference between a voltage provided to thefirst source line SL1 and a voltage applied to the first bit line BL1may increase. That is, since the amount of hot carriers generatedincreases, the program characteristic may be improved. In the case wherea level of a voltage applied to the first word line WL1 decreases, alevel of a voltage applied to the first bit line BL1 may decrease. Also,the influence on another memory cell connected to the first word lineWL1 or the first bit line BL1 may be minimized.

The second memory cell 112 includes a second word line transistor Trw2and a second cell transistor Trc2. The second word line transistor Trw2includes a first terminal (or a first end) connected to the first bitline BL1, a second terminal (or a second end) connected to the firstsource line SL1 through the second cell transistor Trc2, and a controlterminal connected to a second word line WL2. The second cell transistorTrc2 includes a first terminal (or a first end) connected to the firstbit line BL1 through the second word line transistor Trw2, a secondterminal (or a second end) connected to the first source line SL1, and acontrol terminal connected to a second coupling gate line CG2.

The second memory cell 112 is connected with the second word line WL2, asecond coupling gate line CG2, the first erase gate line EG1, the firstsource line SL1, and the first bit line BL1. The second memory cell 112may share the first erase gate line EG1 and the first source line SL1with the first memory cell 111. The second memory cell 112 may bedisposed adjacent to the first memory cell 111 in a column direction.The first memory cell 111 and the second memory cell 112 may have thesame structure, and thus, a detailed description will not be repeatedhere.

FIG. 3 is a sectional view of a first memory cell of FIG. 2.

Referring to FIG. 3, the first memory cell 111 includes a bit lineconnection area BL, a word line connection area WL, a source lineconnection area SL, a coupling gate CG, a floating gate FG, and an erasegate EG. For convenience of description, FIG. 3 will be described withreference to reference numerals or characters of FIG. 2.

The bit line connection area BL and the source line connection area SLmay be formed in a semiconductor substrate. For example, thesemiconductor substrate may be a P-type semiconductor substrate. The bitline connection area BL and the source line connection area SL may be anN-doped area of the semiconductor substrate. The bit line connectionarea BL is connected with the first bit line BL1. A bit line voltage Vblis applied to the bit line connection area BL. The source lineconnection area SL is connected with the first source line SL1. A sourceline voltage Vsl is applied to the source line connection area SL. Achannel area is formed between the bit line connection area BL and thesource line connection area SL. Electrons may flow in the channel area.In a program operation, electrons may transfer from the bit lineconnection area BL to the source line connection area SL.

The word line connection area WL is formed over the channel area. Aninsulating layer may be formed between the word line connection area WLand the semiconductor substrate. The word line connection area WL isconnected with the first word line WL1. A word line voltage Vwl isapplied to the word line connection area WL. The word line connectionarea WL may control an electron transfer or a current flow between thesource line connection area SL and the bit line connection area BL.

The bit line connection area BL, the source line connection area SL, andthe word line connection area WL may form the first word line transistorTrw1. When a level of the word line voltage Vwl exceeds a level of thethreshold voltage of the first word line transistor Trw1, electrons maytransfer in the channel area. In the program operation, a leveldifference between the word line voltage Vwl and the threshold voltagemay correspond to the bit line voltage Vbl.

The floating gate FG is formed not to overlap the word line connectionarea WL on the channel area when viewed from the top. An insulatinglayer may be formed between the word line connection area WL and thesemiconductor substrate. In the program operation, electronstransferring from the bit line connection area BL to the source lineconnection area SL are injected into the floating gate FG.

The coupling gate CG is formed over the floating gate FG. An insulatinglayer may be formed between the coupling gate CG and the floating gateFG. The coupling gate CG is connected with the first coupling gate lineCG1. A coupling gate voltage Vcg is applied to the coupling gate CG. Inthe program operation, the first voltage generated in the high voltagegenerator 165 may be applied to the coupling gate CG. An electric fieldmay be formed between the coupling gate CG and the semiconductorsubstrate by the first voltage, and thus, electrons transferring in thechannel area may be injected into the floating gate FG. The bit lineconnection area BL, the source line connection area SL, the floatinggate FG, and the coupling gate CG may form the first cell transistorTrc1.

The erase gate EG is formed over the source line connection area SL. Aninsulating layer may be formed between the erase gate EG and the sourceline connection area SL. The erase gate EG is disposed adjacent to thefloating gate FG. The erase gate EG is connected with the first erasegate line EG1. An erase gate voltage Veg is applied to the erase gateEG. In an erase operation, the first voltage generated in the highvoltage generator 165 may be applied to the erase gate EG. An electricfield may be formed between the erase gate EG and the floating gate FGby the first voltage, and thus, electrons injected into the floatinggate FG may be tunneled into the erase gate EG.

A threshold voltage of the first word line transistor Trw1 formed by thebit line connection area BL, the source line connection area SL, and theword line connection area WL decreases as an ambient temperatureincreases. At a low temperature, a current flowing between the sourceline connection area SL and the bit line connection area BL decreases asa level of the threshold voltage of the first word line transistor Trw1increases. Accordingly, a program characteristic of the first memorycell 111 becomes deteriorated at the low temperature. At a hightemperature, a level of a voltage applied to the bit line connectionarea BL increases as a level of the threshold voltage decreases. In thiscase, a level of a bit line voltage provided to another memory cell thatshares a bit line with the first memory cell 111 may increase, therebycausing a leakage current.

A voltage applied to a memory cell according to an exemplary embodimentis determined to solve the above problems that may occur based on anambient temperature. The following table 1 shows the bit line voltageVbl, the source line voltage Vsl, the word line voltage Vwl, thecoupling gate voltage Vcg, and the erase gate voltage Veg according toan exemplary embodiment.

TABLE 1 Temperature Vbl Vsl Vwl Vcg Veg Cell state (° C.) (V) (V) (V)(V) (V) Selected memory cell −40 a1 b1 c1 d1 b1 25 a1 b1 c2 d1 b1 125 a1b1 c3 d1 b1 Unselected bit line −40 a2 b1 c1 d1 b1 and selected sourceline 25 a2 b1 c2 d1 b1 125 a2 b1 c3 d1 b1 Selected bit line and −40 a1a1 0 0 0 unselected source line 25 a1 a1 0 0 0 125 a1 a1 0 0 0

Referring to table 1, in the program operation, the first memory cell111 is classified as a selected memory cell, a memory cell connectedwith an unselected bit line and a selected source line, or a memory cellconnected with a selected bit line and an unselected source line. Theselected memory cell means a memory cell that is connected with theselected bit line and the selected source line and corresponds to atarget of the program operation.

In the case where the first memory cell 111 is the selected memory cell,a level of the word line voltage Vwl may decrease as a temperatureincreases. In the case where an ambient temperature is −40° C., a levelof the word line voltage Vwl indicates “c1”. In the case where anambient temperature is 25° C., a level of the word line voltage Vwlindicates “c2” lower than “c1”. In the case where an ambient temperatureis 125° C., a level of the word line voltage Vwl indicates “c3” lowerthan “c2”. Even if a temperature varies, the bit line voltage Vbl havinga uniform level of “a1” may be applied to the first memory cell 111.

The bit line voltage Vbl may be the same as a potential differencebetween the word line voltage Vwl and a threshold voltage of a word linetransistor. A level of the threshold voltage may decrease as an ambienttemperature increases. A level of the threshold voltage may be (c1−a1)when an ambient temperature is −40° C. A level of the threshold voltagemay be (c2−a1) when an ambient temperature is 25° C. A level of thethreshold voltage may be (c3−a1) when an ambient temperature is 125° C.That is, the word line voltage Vwl that varies with a temperature may beapplied to the first memory cell 111 such that the bit line voltage Vblis uniformly maintained.

In a memory cell selected at a low temperature, a level of the word linevoltage Vwl has a higher level. In this case, a decrease of a channelarea due to an increase in the threshold voltage level may be prevented.That is, a program characteristic may be improved at a low temperature.In a memory cell selected at a high temperature, a level of the wordline voltage Vwl has a lower level. In this case, a level of the bitline voltage Vbl, which would otherwise increase due to a decrease ofthe threshold voltage level, may be uniformly maintained. That is, aprogram current may be prevented from being reduced due to a decrease ofa potential difference between the source line voltage Vsl and the bitline voltage Vbl. That is, a program characteristic may be improved at ahigh temperature.

In addition, hot carriers may be injected into a floating gate of aselected memory cell in a program operation. To form a potentialdifference for generating hot carriers, the source line voltage Vsl maybe set to “b1” that is a voltage higher in level than the bit linevoltage Vbl. The coupling gate voltage Vcg may be set to “d1” that is avoltage higher in level than the word line voltage Vwl and the sourceline voltage Vsl such that hot carriers are injected into a floatinggate. Also, the erase gate voltage Veg may be set to “b1” that is avoltage, the level of which is the same as a level of the source linevoltage Vsl.

In the case where the first memory cell 111 is a memory cell connectedwith an unselected bit line and a selected source line, a level of theword line voltage Vwl may decrease as a temperature increases. Similarto the selected memory cell, as an ambient temperature increases to −40°C., 25° C., and 125° C., a level of the word line voltage Vwl decreasesto “c1”, “c2”, and “c3”. The bit line voltage Vbl of an unselected bitline may be set to “a2” that is a suppression voltage to prevent aprogram operation. As the suppression voltage, “a2” is higher in levelthan “a1”. Since the threshold voltage of the first word line transistorTrw1 decreases at a high temperature, a level of the word line voltageVwl decreases as much as the decrement of the threshold voltage level.In this case, an increase of a channel area due to a decrease in thethreshold voltage level may be prevented. That is, a leakage current maybe suppressed by decreasing the threshold voltage level.

A memory cell sharing a source line with a selected memory cell mayshare a word line, a coupling gate line, and an erase gate line with theselected memory cell. Accordingly, a memory cell connected with anunselected bit line and a selected source line may be supplied with thesource line voltage Vsl, the word line voltage Vwl, the coupling gatevoltage Vcg, and the erase gate voltage Veg that are the same as theselected memory cell.

In the case where the first memory cell 111 is connected with a selectedbit line and an unselected source line, voltage levels may not vary witha temperature. A level of the word line voltage Vwl may be set to “0”.The bit line voltage Vbl may be set to “a1” because of sharing a bitline with the selected memory cell. To minimize a leakage current, apotential difference between the bit line voltage Vbl and the sourceline voltage Vsl may be minimized. That is, the source line voltage Vslmay be adjusted to “a1” that is a voltage, the level of which is thesame as a level of the bit line voltage Vbl, such that hot carriers areminimally generated.

A memory cell connected with a selected bit line and an unselectedsource line does not share a word line, a coupling gate line, and anerase gate line. The word line voltage Vwl, the coupling gate voltageVcg, and the erase gate voltage Veg supplied to a memory cell connectedwith a selected bit line and an unselected source line may be “0”.

FIG. 4 is a circuit diagram for describing how a selected memory cell isprogrammed at a selected bit line.

In an exemplary embodiment, memory cells sharing a bit line with aselected memory cell are illustrated in FIG. 4 in addition to theselected memory cell. Here, it is assumed that a selected bit line isthe first bit line BL1 of FIG. 2. For convenience of description, FIG. 4will be described with reference to reference numerals or characters ofFIG. 1. Referring to FIG. 4, a configuration of the flash memory device100, which performs a program operation through the first bit line BL1,includes the first memory cell 111, a first bit line selectiontransistor 131, a transmission gate 141, a data buffer circuit 142, anda pull-down transistor 143.

The first memory cell 111 is a memory cell selected for the programoperation. A source line connected to the first memory cell 111 providesa selected source line voltage Vssl to the first memory cell 111. Theselected source line voltage Vssl is the second voltage generated fromthe middle voltage generator 166. The first memory cell 111 may besupplied with the coupling gate voltage Vcg being a high voltage for theprogram operation. The first memory cell 111 may be supplied with theword line voltage Vwl. In this case, a voltage level of the first bitline BL1 may be the same as a potential difference between the word linevoltage Vwl and a threshold voltage of the first word line transistorTrw1. A program cell current iPC may flow through the first memory cell111 based on the selected source line voltage Vssl, the word linevoltage Vwl, and a voltage of the first bit line BL1.

The memory device 100 may include third to m-th memory cells 113, 114 .. . 11 m connected to the first bit line BL1. It is assumed that thethird to m-th memory cells 113 to 11 m are not selected by the rowdecoder 120 in the program operation. The third to m-th memory cells 113to 11 m may share the first bit line BL1 with the first memory cell 111and may be respectively connected to source lines that are differentfrom a source line connected to the first memory cell 111. The third tom-th memory cells 113 to 11 m may be respectively connected to acoupling gate line connected to the first memory cell 111 and differentgate lines. The third to m-th memory cells 113 to 11 m may berespectively connected to word lines that are different from a word lineconnected to the first memory cell 111. A word line voltage and acoupling gate voltage of each of the third to m-th memory cells 113 to11 m may be “0”.

A bit line voltage level of each of the third to m-th memory cells 113to 11 m may be the same as a difference between the word line voltageVwl applied to the first memory cell 111 and a threshold voltage of thefirst word line transistor Trw1. The third to m-th memory cells 113 to11 m may be supplied with an unselected source line voltage Vus1 fromcorresponding source lines. Even if a word line voltage is “0”, aleakage current iLCK may be generated according to a potentialdifference between a bit line voltage and the unselected source linevoltage Vus1.

A program current iPGM may be the same as a sum of the program cellcurrent iPC flowing to the first memory cell 111 and a leakage currentiLCK generated by the third to m-th memory cells 113 to 11 m. In thecase where a bit line voltage is smaller in level than the unselectedsource line voltage Vus1, the leak current may flow from the unselectedsource line to the first bit line BL1. In this case, since the programcell current iPC decreases, a program characteristic of the first memorycell 111 may become deteriorated. In the case where a bit line voltageis greater in level than the unselected source line voltage Vus1, theleak current may flow from the first bit line BL1 to the unselectedsource line. In this case, since the program cell current iPC increases,power consumption may increase.

As an ambient temperature varies, a threshold voltage of a word linetransistor may vary, thereby causing a change in a voltage level of abit line connected with a selected memory cell. That is, in the casewhere the unselected source line voltage Vus1 has a fixed voltage level,if a bit line voltage varies with a temperature, the probability thatthe leakage current iLCK is generated is high. Accordingly, a voltagelevel of the unselected source line voltage Vus1 according to anexemplary embodiment may be the same as a bit line voltage level. Inthis case, the leakage current iLCK may be minimized, and thus, theprogram characteristic may be improved.

The first bit line selection transistor 131 may be included in the bitline selection circuit 130. The bit line selection circuit 130 mayinclude a plurality of bit line selection transistors connected with aplurality of bit lines. The first bit line selection transistor 131includes a first terminal connected with the first bit line BL1, asecond terminal connected with the transmission gate 141, and a controlterminal receiving a bit line selection signal BS. The first bit lineselection transistor 131 may select the first bit line BL1 in responseto the bit line selection signal BS such that the program current iPGMflows therethrough.

The transmission gate 141 may be included in the data input/outputcircuit 140. The transmission gate 141 may include different types oftransistors connected in parallel. For example, the transmission gate141 may include an NMOS transistor and a PMOS transistor connected inparallel. The NMOS transistor includes a first terminal connected withthe second terminal of the first bit line selection transistor 131, asecond terminal connected with the data buffer circuit 142, and acontrol terminal receiving a program signal PGM. The PMOS transistorincludes a first terminal connected with the second terminal of thefirst bit line selection transistor 131, a second terminal connectedwith the data buffer circuit 142, and a control terminal receiving aninverted program signal PGM′. When the NMOS transistor receives theprogram signal PGM or the PMOS transistor receives the inverted programsignal PGM′, the transmission gate 141 may output the program currentiPGM such that the program operation is performed.

The data buffer circuit 142 may be included in the data input/outputcircuit 140. The data buffer circuit 142 may output the program currentiPGM such that a program operation corresponding to a received datainput signal DIN is performed. The data buffer circuit 142 may include aCMOS inverter. The CMOS inverter may include a PMOS transistor and anNMOS transistor receiving the data input signal DIN. The PMOS transistormay include a first terminal receiving a supply voltage VDD, a secondterminal connected with the transmission gate 141, and a controlterminal receiving the data input signal DIN. The NMOS transistor mayinclude a first terminal connected with the transmission gate 141, asecond terminal connected with the pull-down transistor 143, and acontrol terminal receiving the data input signal DIN. The data buffercircuit 142 may delay a program operation during a given time from apoint in time to receive the data input signal DIN.

The pull-down transistor 143 may be included in the data input/outputcircuit 140. The pull-down transistor 143 includes a first terminalconnected with the data buffer circuit 142, a second terminal grounded,and a control terminal receiving a pull-down signal PD. When thepull-down signal PD is received, the program current iPGM may flowthrough the pull-down transistor 143. An active pull-down function maybe performed in the data input/output circuit 140 by using the pull-downtransistor 143.

FIG. 5 is a block diagram illustrating an exemplary configuration of abias generator of FIG. 1.

Referring to FIG. 5, the bias generator 160 includes a temperaturedetecting circuit 161, a bias controller 162, a word line voltagegenerator 163, and an unselected source line voltage generator 164.Although not illustrated in FIG. 5, the bias generator 160 may furtherinclude the high voltage generator 165 and the middle voltage generator166 of FIG. 1.

The temperature detecting circuit 161 detects an ambient temperature.The temperature detecting circuit 161 may include a temperaturedetecting element having a characteristic variable with a temperaturefor the purpose of detecting an ambient temperature. The temperaturedetecting circuit 161 may generate a temperature detection signal TS forchanging the word line voltage Vwl or the unselected source line voltageVus1 depending on a change in an ambient temperature.

The bias controller 162 controls a level of the word line voltage Vwlbased on the detected temperature. The bias controller 162 may receivethe temperature detection signal TS from the temperature detectingcircuit 161. The bias controller 162 may determine an ambienttemperature based on the temperature detection signal TS and may allowthe word line voltage generator 163 to adjust the word line voltage Vwlto be applied to the selected word line in a program operation. The biascontroller 162 may generate a word line voltage control signal WCS forcontrolling the word line voltage generator 163. The bias controller 162is illustrated in FIG. 5 as a separate component from the temperaturedetecting circuit 161, but the disclosure may not be limited thereto.For example, the bias controller 162 may be included in the temperaturedetecting circuit 161.

The word line voltage control signal WCS may be provided to the wordline voltage generator 163 such that a level of the word line voltageVwl is adjusted. The bias controller 162 may program the word linevoltage control signal WCS such that the level of the word line voltageVwl is adjusted according to the detected temperature. The biascontroller 162 may determine a level of a threshold voltage of a wordline transistor, which corresponds to the detected temperature. Forexample, information about a level of a threshold voltage of a word linetransistor, which corresponds to the detected temperature, may be inadvance set in the bias controller 162, and the bias controller 162 mayselect threshold voltage level information corresponding to thetemperature detection signal TS. The bias controller 162 may generatethe word line voltage control signal WCS for adjusting the word linevoltage Vwl depending on the selected threshold voltage levelinformation.

The word line voltage generator 163 generates the word line voltage Vwlto be applied to a selected word line in the program operation. The wordline voltage generator 163 may receive the word line voltage controlsignal WCS from the bias controller 162. The word line voltage generator163 may adjust a level of the word line voltage Vwl in response to theword line voltage control signal WCS. For example, the word line voltagegenerator 163 may include a variable resistor and may adjust a level ofthe word line voltage Vwl by adjusting a resistance value of thevariable resistor in response to the word line voltage control signalWCS. The word line voltage Vwl thus generated is provided to the rowdecoder 120 of FIG. 1. The row decoder 120 provides the word linevoltage Vwl to a selected word line in the program operation.

The word line voltage generator 163 may generate the word line voltageVwl of a voltage level that becomes lower as an ambient temperatureincreases. The word line voltage generator 163 may decrease a level ofthe word line voltage Vwl as much as a decrement, which corresponds toan increment of a temperature, of a threshold voltage level of a memorycell. Accordingly, a potential difference between the word line voltageVwl and a threshold voltage may be uniformly maintained. That is, aselected bit line voltage may be uniformly maintained in the programoperation.

The unselected source line voltage generator 164 generates theunselected source line voltage Vus1 to be applied to an unselectedsource line in the program operation. The unselected source line voltagegenerator 164 may receive the word line voltage Vwl from the word linevoltage generator 163. The unselected source line voltage generator 164may generate the unselected source line voltage Vus1 having the samevoltage level as the selected bit line voltage.

The unselected source line voltage generator 164 may include atransistor having the same characteristic as a transistor of a memorycell to be programmed. That is, in the unselected source line voltagegenerator 164, the same environment as a memory cell may be implementedby using a transistor having the same threshold voltage as a word linetransistor of the memory cell. Accordingly, the same voltage as theselected bit line voltage may be generated without detecting theselected bit line voltage. The unselected source line voltage Vus1 thusgenerated is provided to the row decoder 120 of FIG. 1. The row decoder120 provides the unselected source line voltage Vus1 to an unselectedsource line.

FIG. 6 is a view illustrating an exemplary configuration of atemperature detecting circuit of FIG. 5.

The temperature detecting circuit 161 of FIG. 6 may be understood as oneexemplification for detecting an ambient temperature. The temperaturedetecting circuit 161 may detect an ambient temperature in variousmanners and may not be limited to the embodiment of FIG. 6.

Referring to FIG. 6, the temperature detecting circuit 161 includes afirst amplifier Amp1, first and second transistors TR1 and TR2, abipolar transistor (or bipolar junction transistor) BJT, first to thirdcomparators Cmp1 to Cmp3, first to third delay circuits Dly1 to Dly3,and a temperature coding circuit 161_1.

The first amplifier Amp 1 may amplify the reference voltage Vref. Thefirst amplifier Amp1 may include a first input terminal receiving thereference voltage Vref, a second input terminal connected with a thirdnode n3, and an output terminal connected with control terminals of thefirst and second transistors TR1 and TR2. A voltage level of a firstnode n1 and a voltage level of a second node n2 may be controlled to begreater than a level of the reference voltage Vref by the firstamplifier Amp1.

The first transistor TR1 includes a first terminal receiving a supplyvoltage VDD, a second terminal connected with the first node n1, and acontrol terminal connected with the output terminal of the firstamplifier Amp1. The second transistor TR2 includes a first terminalreceiving the supply voltage VDD, a second terminal connected with afourth node n4, and a control terminal connected with the outputterminal of the first amplifier Amp1. The first and second transistorsTR1 and TR2 may be PMOS transistors. When the reference voltage Vref isinput to the first amplifier Amp1, a reference current may flow throughthe first transistor TR1, and a variable temperature current may flowthrough the second transistor TR2.

First to third resistors R1 to R3 may be connected in series to dividethe amplified reference voltage. The first resistor R1 includes a firstterminal connected to the first node n1 and a second terminal connectedto the second node n2. The second resistor R2 includes a first terminalconnected to the second node n2 and a second terminal connected to thethird node n3. The third resistor R3 includes a first terminal connectedto the third node n3 and a second terminal grounded. An example isillustrated in FIG. 6 as three resistors are connected in series, butthe number of resistors connected in series may not be limited.

The bipolar transistor BJT may have a great resistance value as atemperature increases. The bipolar transistor BJT is connected to thefourth node n4. The bipolar transistor BJT may be a PNP bipolartransistor. The variable temperature current varies with a change in aresistance value of the bipolar transistor BJT, and thus, a voltage ofthe fourth node n4 varies. A voltage of the fourth node n4 may decreaseas an ambient temperature increases. The bipolar transistor BJT isillustrated in FIG. 6 as a temperature detecting element. However, thedisclosure may not be limited thereto. For example, various elements,characteristics of which vary with a temperature, may be used instead ofthe bipolar transistor BJT.

The first comparator Cmp1 may amplify a potential difference between thefirst node n1 and the fourth node n4 to compare the voltage of the firstnode n1 with the voltage of the fourth node n4. The first comparatorCmp1 may include a first input terminal connected to the first node n1,a second input terminal connected with the fourth node n4, and an outputterminal connected with the first delay circuit Dly1. The firstcomparator Cmp1 may be configured to output a comparison voltage basedon comparing the voltage of the first node n1 with the voltage of thefourth node n4. For example, the first comparator Cmp1 may be configuredto output the comparison voltage having high level when a level of thevoltage of the fourth node n4 is higher than a level of the voltage ofthe first node n1. The first comparator Cmp1 may be configured to outputthe comparison voltage having low level when the level of the voltage ofthe fourth node n4 is lower than a level of the voltage of the firstnode n1.

The second comparator Cmp2 may amplify a potential difference betweenthe second node n2 and the fourth node n4 to compare the voltage of thesecond node n2 with the voltage of the fourth node n4. The secondamplifier Cmp2 may include a first input terminal connected to thesecond node n2, a second input terminal connected with the fourth noden4, and an output terminal connected with the second delay circuit Dly2.The second comparator Cmp2 may be configured to output a comparisonvoltage based on comparing the voltage of the second node n2 with thevoltage of the fourth node n4. The third comparator Cmp3 may amplify apotential difference between the third node n3 and the fourth node n4 tocompare the voltage of the third node n3 with the voltage of the fourthnode n4. The third amplifier Cmp3 may include a first input terminalconnected to the third node n3, a second input terminal connected withthe fourth node n4, and an output terminal connected with the thirddelay circuit Dly3. The third comparator Cmp3 may be configured tooutput a comparison voltage based on comparing the voltage of the thirdnode n3 with the voltage of the fourth node n4.

The first delay circuit Dly1 may delay the comparison voltage from thefirst comparator Cmp1 and may output the delayed voltage to thetemperature coding circuit 161_1. The second delay circuit Dly2 maydelay the comparison voltage from the second comparator Cmp2 and mayoutput the delayed voltage to the temperature coding circuit 161_1. Thethird delay circuit Dly3 may delay the comparison voltage from the thirdcomparator Cmp3 and may output the delayed voltage to the temperaturecoding circuit 161_1.

The temperature coding circuit 161_1 receives voltages output from thefirst to third delay circuits Dly1 to Dly3. Levels of voltages that areoutput by the first to third delay circuits Dly1 to Dly3 may vary with achange in an ambient temperature. The temperature coding circuit 161_1generates the temperature detection signal TS based on the receivedvoltages. The temperature detection signal TS may be provided to thebias controller 162 of FIG. 5. The temperature coding circuit 161_1 maycode the temperature detection signal TS to a signal that the biascontroller 162 is able to process, based on the detected temperature.

FIG. 7 is a graph for describing a change in a voltage according to atemperature in a temperature detecting circuit of FIG. 6.

In FIG. 7, a horizontal axis represents a temperature, and a verticalaxis represents a voltage. A graph of FIG. 7 shows voltage levels offirst to fourth node voltages Vn1 to Vn4 according to a change in atemperature. The first to fourth node voltages Vn1 to Vn4 indicatevoltages of the first to fourth nodes n1 to n4 of FIG. 6, respectively.For convenience of description, FIG. 7 will be described with referenceto reference numerals or characters of FIG. 6.

The first to third node voltages Vn1 to Vn3 are voltages divided by thefirst to third resistors R1 to R3 connected in series. The first nodevoltage Vn1 has a voltage level higher than the second node voltage Vn2,and the second node voltage Vn2 has a voltage level higher than thethird node voltage Vn3. The fourth node voltage Vn4 varies with acharacteristic change of the bipolar transistor BJT due to a temperaturechange. The fourth node voltage Vn4 decreases according to an increasein an ambient temperature.

The temperature detecting circuit 161 may generate the temperaturedetection signal TS based on voltages output from the first to thirdcomparators Cmp1 to Cmp3. The first comparator Cmp1 may compare thefirst node voltage Vn1 and the fourth node voltage Vn4. The secondcomparator Cmp2 may compare the second node voltage Vn2 and the fourthnode voltage Vn4. The third comparator Cmp3 may compare the third nodevoltage Vn3 and the fourth node voltage Vn4. The bias controller 162 mayallow the word line voltage generator 163 to change voltage levels ofthe selected word line voltage Vwl and the unselected source linevoltage Vus1 for a program operation, based on the above-describedresults.

FIG. 8 is a view illustrating an exemplary configuration of a word linevoltage generator of FIG. 5.

The word line voltage generator 163 of FIG. 8 may be understood as oneexemplification for generating a selected word line voltage Vwl in aprogram operation. The word line voltage generator 163 may generate theword line voltage Vwl in various manners. Referring to FIG. 8, the wordline voltage generator 163 may include a second amplifier Amp2, a thirdtransistor TR3, and a variable resistor unit 163_1.

The second amplifier Amp2 may amplify the reference voltage Vref. Thesecond amplifier Amp2 may include a first input terminal receiving thereference voltage Vref, a second input terminal connected with thevariable resistor unit 163_1, and an output terminal connected with acontrol terminal of the third transistor TR3. A voltage applied from thethird transistor TR3 to the variable resistor unit 163_1 may beamplified by the second amplifier Amp2.

The third transistor TR3 includes a first terminal receiving the supplyvoltage VDD, a second terminal connected with the variable resistor unit163_1, and a control terminal connected with the output terminal of thesecond amplifier Amp2. The third transistor TR3 may be a PMOStransistor. When the reference voltage Vref is input to the secondamplifier Amp2, a variable reference current for generating the wordline voltage Vwl may flow through the third transistor TR3.

The variable resistor unit 163_1 may include at least one variableresistor, the resistance value of which is changed according to the wordline voltage control signal WCS, and an output terminal to output theword line voltage Vwl. For example, the variable resistor may be formedbetween the second terminal of the third transistor TR3 and the secondinput terminal of the second amplifier Amp2. Alternatively, the variableresistor may be formed between the second terminal of the thirdtransistor TR3 and the output terminal of the variable resistor unit163_1. Alternatively, the variable resistor may be formed between thesecond terminal of the second amplifier Amp2 and a ground. That is, thevariable resistor unit 163_1 may be configured to output the word linevoltage Vwl that varies with a resistance value of the variableresistor.

The variable resistor unit 163_1 may generate the word line voltage Vwlin response to the word line voltage control signal WCS. A resistancevalue of the variable resistor included in the variable resistor unit163_1 may be determined according to the word line voltage controlsignal WCS. Since the word line voltage control signal WCS indicates anambient temperature, a change in the resistance value of the variableresistor depends on a change in a temperature. The resistance value ofthe variable resistor may be determined based on a change in a thresholdvoltage of a memory cell included in the memory cell array 110 of FIG. 1when a temperature varies.

Based on a change in the resistance value of the variable resistor, thevariable resistor unit 163_1 may divide or amplify the reference voltageVref to generate the word line voltage Vwl. The word line voltage Vwlthus generated is provided to a selected memory cell in the programoperation. A variation in a threshold voltage level of a selected memorycell due to a temperature change may be the same as a variation in thelevel of the word line voltage Vwl generated by the variable resistorunit 163_1 or may be within a specific range.

FIG. 9 is a view illustrating an exemplary configuration of anunselected source line voltage generator of FIG. 5.

The unselected source line voltage generator 164 of FIG. 9 may beunderstood as one exemplification for generating the unselected sourceline voltage Vus1. The unselected source line voltage generator 164 maygenerate the unselected source line voltage Vus1 in various manners.Referring to FIG. 9, the unselected source line voltage generator 164may include fourth to sixth transistors TR4 to TR6.

The fourth transistor TR4 may include a first terminal receiving thesupply voltage VDD, a second terminal connected with a first terminal ofthe fifth transistor TR5, and a control terminal receiving the invertedprogram signal PGM′. The fourth transistor TR4 may be a PMOS transistor.In a program operation, the fourth transistor TR4 may be saturated, andthus, the unselected source line voltage generator 164 may be driven.Unlike the configuration of FIG. 9, the fourth transistor TR4 may beomitted.

The fifth transistor TR5 includes the first terminal connected with thesecond terminal of the fourth transistor TR4, a second terminaloutputting the unselected source line voltage Vus1, and a controlterminal receiving the word line voltage Vwl. The control terminal ofthe fifth transistor TR5 may be supplied with the word line voltage Vwloutput from the word line voltage generator 163 of FIG. 5. The fifthtransistor TR5 may have the same characteristic as a transistor of amemory cell. That is, the fifth transistor TR5 may have the samethreshold voltage as a memory cell. A voltage of the second terminal ofthe fifth transistor TR5 may be the same as a difference between theword line voltage Vwl and a threshold voltage. Accordingly, a potentialdifference between the word line voltage Vwl and the threshold voltagemay be the same as the unselected source line voltage Vus1.

In the program operation, a voltage level of a bit line connected with aselected memory cell may be the same as a difference between the wordline voltage Vwl applied to a selected word line and the thresholdvoltage. Accordingly, the unselected source line voltage Vus1 having avoltage level that is the same as a voltage level of a selected bit linemay be output. That is, by the fifth transistor TR5, the unselectedsource line voltage Vus1 may be controlled to have a voltage level of aselected bit line for a program operation.

The sixth transistor TR6 may include a first terminal connected with thesecond terminal of the fifth transistor TR5, a second terminal grounded,and a control terminal receiving the pull-down signal PD. When thepull-down signal PD is received, the program current iPGM may flowbetween the first and second terminals of the sixth transistor TR6. Theprogram current iPGM may be the same as a current flowing to a selectedbit line in the program operation. The sixth transistor TR6 may have thesame characteristic as the pull-down transistor 143 of FIG. 4.

FIG. 10 is a graph for describing a relationship between a word linevoltage, an unselected source line voltage, and a selected bit linevoltage generated by a bias generator of FIG. 5.

In FIG. 10, a horizontal axis represents a temperature, and a verticalaxis represents a voltage. The graph of FIG. 10 shows levels of the wordline voltage Vwl, the unselected source line voltage Vus1, and theselected bit line voltage Vbl when a temperature varies. A bold solidline indicates the word line voltage Vwl. A solid line indicates theunselected source line voltage Vus1. A dotted line indicates the bitline voltage Vbl. For convenience of description, FIG. 10 will bedescribed with reference to reference numerals or characters of FIG. 5.

The word line voltage Vwl is generated by the word line voltagegenerator 163. A threshold voltage level of a memory cell decreases as atemperature increases. The word line voltage generator 163 may decreasea level of the word line voltage Vwl as much as a decrement of thethreshold voltage of the memory cell. For example, the word line voltagegenerator 163 may stepwise decrease a level of the word line voltage Vwlas a temperature increases. When the decrement of the threshold voltagelevel of the memory cell due to the increase in the temperature exceedsa specific range, the word line voltage generator 163 may decrease alevel of the word line voltage Vwl.

The selected bit line voltage Vbl may have a voltage level correspondingto a difference between the word line voltage Vwl and the thresholdvoltage of the memory cell in a program operation. As described above,the threshold voltage level may decrease as a temperature increases, anda level of the word line voltage Vwl may be stepwise decreased by theword line voltage generator 163 as a temperature increases. Accordingly,a level of the selected bit line voltage Vbl has a tooth waveform. Adifference between the minimum value and the maximum value of theselected bit line voltage Vbl may be within a certain range (e.g.,reference range).

A level of the unselected source line voltage Vus1 may be the same as alevel of the bit line voltage Vbl. The unselected source line voltagegenerator 164 may receive the word line voltage Vwl and may output avoltage corresponding to a difference between the word line voltage Vwland the threshold voltage as the unselected source line voltage Vus1.Accordingly, the unselected source line voltage Vus1 may have a toothwaveform that is the same as the selected bit line voltage Vbl.

To sum up, in the program operation, the bias generator 160 generatesthe word line voltage Vwl that increases as a temperature decreases.That is, it may be possible to prevent a program characteristic fromweakening due to a decrease in a channel area according to an increasein a threshold voltage of a word line transistor included in a memorycell at a low temperature. The bias generator 160 generates the wordline voltage Vwl that decreases as a temperature increases. That is, ata high temperature, a bit line voltage may increase as the thresholdvoltage of the word line transistor decreases, and thus, a potentialdifference between a source line voltage and a bit line voltage maydecrease. This may mean that the amount of hot carriers is preventedfrom decreasing.

The bias generator 160 may minimize a potential difference between a bitline connection area and a source line connection area in a memory cellconnected with a selected bit line and an unselected source line. Thatis, in the program operation, there may be prevented a leakage currentgenerated at a memory cell connected with an unselected source line.Also, in a memory cell connected with an unselected bit line and aselected source line, the bias generator 160 may decrease the word linevoltage Vwl when a temperature increases, thereby reducing a leakagecurrent. That is, the probability that a leakage current is generateddue to an increase in a channel area when a word line voltage decreasesmay become lower. Accordingly, it may be possible to prevent electronsfrom being injected or ejected into or from a floating gate of anunselected memory cell.

FIG. 11 is a flowchart of a program method of a flash memory deviceaccording to an exemplary embodiment.

Referring to FIG. 11, a program method of a flash memory device isperformed in the flash memory device 100 of FIG. 1. For convenience ofdescription, the flowchart of FIG. 11 will be described with referenceto reference numerals or characters of FIGS. 1 and 5.

In operation S110, the bias generator 160 senses an ambient temperatureof the memory device 100. The ambient temperature may be detected by thetemperature detecting circuit 161 included in the bias generator 160.The temperature detecting circuit 161 may detect an ambient temperatureand may provide the temperature detection signal TS to the biascontroller 162. The bias controller 162 may provide the word linevoltage control signal WCS to the word line voltage generator 163 basedon the temperature detection signal TS.

In operation S120, the word line voltage generator 163 included in thebias generator 160 generates the word line voltage Vwl based on the wordline voltage control signal WCS. The word line voltage generator 163generates the word line voltage Vwl based on the detected temperature.The word line voltage generator 163 may adjust the word line voltage Vwlso as to have a voltage level that decreases as the ambient temperatureincreases. The word line voltage generator 163 may adjust the word linevoltage Vwl such that a level change in the word line voltage Vwl at achange in a temperature is the same as a level change in a thresholdvoltage of a word line transistor or is within a specific range. Theword line voltage generator 163 may adjust the word line voltage Vwl byusing a variable resistor unit having a variable resistance valuedepending on the detected temperature. The word line voltage Vwl isprovided to the row decoder 120.

In operation S130, the unselected source line voltage generator 164included in the bias generator 160 generates the unselected source linevoltage Vus1. The unselected source line voltage generator 164 maygenerate the unselected source line voltage Vus1 based on the word linevoltage Vwl adjusted in operation S120. The unselected source linevoltage generator 164 may adjust the unselected source line voltage Vus1so as to have a voltage level the same as a level of a selected bit linevoltage. That is, the unselected source line voltage generator 164 mayadjust the unselected source line voltage Vus1 so as to have a voltagelevel corresponding to a difference between the word line voltage Vwland a threshold voltage of a word line transistor. The unselected sourceline voltage Vus1 is provided to the row decoder 120.

In operation S140, the row decoder 120 applies the word line voltage Vwlto a memory cell connected to a selected source line. The memory cellconnected to the selected source line includes a memory cell connectedwith the selected source line and a selected bit line for a programoperation. Also, the memory cell connected to the selected source lineincludes a memory cell connected with the selected source line and anunselected bit line. The row decoder 120 may select a source line forthe program operation under control of the control circuit 150. The bitline selection circuit 130 may select a bit line for the programoperation under control of the control circuit 150. Under control of thecontrol circuit 150, the row decoder 120 may select a word line for theprogram operation and may apply the word line voltage Vwl to theselected word line. The row decoder 120 may not apply a voltage to anunselected word line.

In the memory cells to which the word line voltage Vwl is applied, avoltage level of a selected bit line may be the same as a differencebetween the word line voltage Vwl and the threshold voltage of the wordline transistor. In the memory cells to which the word line voltage Vwlis applied, a suppression voltage may be applied to an unselected bitline. The bit line selection circuit 130 may apply the suppressionvoltage to the unselected bit line to inhibit a program operation of amemory cell connected to the unselected bit line.

In operation S150, the row decoder 120 applies an unselected source linevoltage to a memory cell connected to an unselected source line. The rowdecoder 120 selects a source line for the program operation and appliesthe unselected source line voltage Vus1 to the unselected source line.Memory cells connected with the selected bit line and the unselectedsource line may have the same potential difference between a bit lineconnection area and a source line connection area. The row decoder 120may apply a selected source line voltage to the selected source line,and the selected source line voltage may be a voltage generated in themiddle voltage generator 166.

Although not illustrated in FIG. 11, the program method of the flashmemory device may further include applying a voltage generated in thehigh voltage generator 165 to a memory cell connected to a selectedcoupling gate line. Also, the program method of the flash memory devicemay further include applying a voltage generated in the middle voltagegenerator 166 to a memory cell connected to a selected erase gate line.

FIG. 12 is an exemplary block diagram of a memory system including aflash memory device of FIG. 1.

Referring to FIG. 12, a memory system 1000 may include the flash memorydevice 100, a memory controller 200, a central processing unit (CPU)300, a code memory 400, a host interface 500, and a bus 600. The memorysystem 1000 of FIG. 12 may be an embedded memory system in which aprogram and a logic circuit for an access to the flash memory device 100are integrated in a single chip.

The memory controller 200 controls the flash memory device 100. Thememory controller 200 may receive a program command and may control theflash memory device 100 such that program data are stored in the flashmemory device 100. Also, the memory controller 200 may receive a readcommand and may control the flash memory device 100 such that a readoperation is performed. The memory controller 200 may receive an erasecommand and may control the flash memory device 100 such that an eraseoperation is performed.

The central processing unit 300 may control overall operations of thememory system 1000. For example, the central processing unit 300 maygenerate a command for performing a program operation, a read operation,or an erase operation in response to an external request. Also, thecentral processing unit 300 may control each component of the memorysystem 1000 such that various operations are performed.

The code memory 400 may store a variety of code information foraccessing the flash memory device 100 or driving the flash memory device100. The central processing unit 300 may control the flash memory device100 and the memory controller 200 based on the pieces of codeinformation stored in the code memory 400. The code memory 400 mayinclude a nonvolatile memory device.

The host interface 500 may provide an interface between a host and thememory system 1000. The host interface 500 may communicate with the hostbased on at least one of various interface protocols such as universalserial bus (USB), small computer small interface (SCSI), peripheralcomponent interconnect (PCI) express, advanced technology attachment(ATA), parallel ATA (PATA), serial ATA (SATA), serial attached SCSI(SAS), and the like.

The bus 600 may provide a communication path between the memorycontroller 200, the central processing unit 300, the code memory 400,and the host interface 500 of the memory system 1000. The respectivecomponents of the memory system 1000 may exchange information with eachother through the bus 600.

According to exemplary embodiments, a flash memory device and a programmethod thereof adjust a word line voltage and an unselected source linevoltage based on a temperature change, thereby improving a programcharacteristic and minimizing a leakage current of an unselected memorycell.

As is traditional in the field of the inventive concepts, exampleembodiments are described, and illustrated in the drawings, in terms offunctional blocks, units and/or modules. Those skilled in the art willappreciate that these blocks, units and/or modules are physicallyimplemented by electronic (or optical) circuits such as logic circuits,discrete components, microprocessors, hard-wired circuits, memoryelements, wiring connections, and the like, which may be formed usingsemiconductor-based fabrication techniques or other manufacturingtechnologies. In the case of the blocks, units and/or modules beingimplemented by microprocessors or similar, they may be programmed usingsoftware (e.g., microcode) to perform various functions discussed hereinand may optionally be driven by firmware and/or software. Alternatively,each block, unit and/or module may be implemented by dedicated hardware,or as a combination of dedicated hardware to perform some functions anda processor (e.g., one or more programmed microprocessors and associatedcircuitry) to perform other functions. Also, each block, unit and/ormodule of the example embodiments may be physically separated into twoor more interacting and discrete blocks, units and/or modules withoutdeparting from the scope of the inventive concepts. Further, the blocks,units and/or modules of the example embodiments may be physicallycombined into more complex blocks, units and/or modules withoutdeparting from the scope of the inventive concepts.

While the inventive concept has been described with reference toexemplary embodiments thereof, it will be apparent to those of ordinaryskill in the art that various changes and modifications may be madethereto without departing from the spirit and scope of the inventiveconcept as set forth in the following claims.

What is claimed is:
 1. A flash memory device comprising: a first memorycell comprising a first cell transistor, the first cell transistor beingconnected to a selected bit line through a first word line transistorand connected with a selected source line; a second memory cellcomprising a second cell transistor, the second cell transistor beingconnected to the selected bit line through a second word line transistorand connected to an unselected source line; a row decoder configured tocontrol a word line voltage to be applied to a first word line connectedto the first word line transistor, and configured to control a selectedsource line voltage to be applied to the selected source line and anunselected source line voltage to be applied to the unselected sourceline; and a bias generator configured to generate the word line voltagebased on a threshold voltage of the first word line transistor, thethreshold voltage changing with an ambient temperature, and configuredto generate the unselected source line voltage based on a voltage levelof the selected bit line.
 2. The flash memory device of claim 1, whereinthe bias generator is configured to generate the word line voltage tohave a level that is decreased in response to an increase in the ambienttemperature.
 3. The flash memory device of claim 1, wherein the biasgenerator is configured to generate the word line voltage to have alevel that is adjusted based on a variation in a level of the thresholdvoltage in response to a change in the ambient temperature.
 4. The flashmemory device of claim 1, wherein the bias generator is configured togenerate the unselected source line voltage, a level of which is thesame as the voltage level of the selected bit line.
 5. The flash memorydevice of claim 1, wherein the bias generator comprises: a temperaturedetecting circuit configured to detect the ambient temperature; a wordline voltage generator configured to adjust a level of the word linevoltage based on the detected temperature; and an unselected source linevoltage generator configured to generate the unselected source linevoltage based on the level of the word line voltage that is adjusted bythe word line voltage generator.
 6. The flash memory device of claim 5,wherein the word line voltage generator comprises: a variable resistorunit having a resistance value varying with a magnitude of the detectedtemperature, the variable resistor unit configured to adjust the levelof the word line voltage based on the resistance value.
 7. The flashmemory device of claim 5, wherein the bias generator further comprises:a bias controller configured to control the word line voltage generatorbased on a temperature detection signal generated by the temperaturedetecting circuit.
 8. The flash memory device of claim 1, wherein thebias generator is configured to generate the selected source linevoltage, a level of which is higher than the voltage level of theselected bit line, and wherein the row decoder is configured to receivethe word line voltage, the selected source line voltage, and theunselected source line voltage from the bias generator, apply the wordline voltage and the selected source line voltage to the first memorycell, and apply the unselected source line voltage to the second memorycell.
 9. The flash memory device of claim 1, wherein a memory cell arrayin which the first memory cell and the second memory cell are includedis of a NOR flash type.
 10. A flash memory device comprising: a firstmemory cell connected to a selected bit line and a selected source line;a second memory cell connected to the selected bit line and anunselected source line; a row decoder configured to apply a selectedsource line voltage to the selected source line and an unselected sourceline voltage to the unselected source line; and a bias generatorconfigured to generate the unselected source line voltage based on avoltage level of the selected bit line.
 11. The flash memory device ofclaim 10, wherein the first memory cell comprises: a first word linetransistor comprising a first terminal connected to the selected bitline, a second terminal connected to the selected source line, and acontrol terminal connected to a first word line, and wherein the secondmemory cell comprises: a second word line transistor comprising a firstterminal connected to the selected bit line, a second terminal connectedto the unselected source line, and a control terminal connected to asecond word line.
 12. The flash memory device of claim 11, wherein thebias generator is configured to adjust a level of a word line voltage,to be applied to the first word line, based on a threshold voltage ofthe first word line transistor, the threshold voltage changing with anambient temperature.
 13. The flash memory device of claim 11, whereinthe bias generator is configured to adjust a level of a word linevoltage to be applied to the first word line such that the voltage levelof the selected bit line is within a reference range, and configured toadjust a level of the unselected source line voltage to be within thereference range based on the adjusted level of the word line voltage.14. The flash memory device of claim 11, wherein the bias generator isconfigured to stepwise decrease a level of a word line voltage to beapplied to the first word line in response to an increase of an ambienttemperature.
 15. The flash memory device of claim 11, wherein the biasgenerator comprises: a temperature detecting circuit configured todetect an ambient temperature; a word line voltage generator configuredto adjust a level of a word line voltage to be applied to the first wordline based on the detected temperature; and an unselected source linevoltage generator configured to adjust a level of the unselected sourceline voltage based on the word line voltage.
 16. The flash memory deviceof claim 15, wherein the unselected source line voltage generatorcomprises: a transistor comprising a control terminal configured toreceive the word line voltage, the transistor having a threshold voltagethat is equal to a threshold voltage of the first word line transistor,and wherein the transistor is configured to output the unselected sourceline voltage, a level of which corresponds to a difference between theword line voltage and the threshold voltage of the transistor.
 17. Theflash memory device of claim 10, wherein the bias generator isconfigured to generate the unselected source line voltage, a level ofwhich is the same as the voltage level of the selected bit line.
 18. Aprogram method of a flash memory device which comprises a memory cellarray, the method comprising: detecting an ambient temperature;generating a word line voltage based on the detected ambienttemperature; generating an unselected source line voltage based on theword line voltage and a voltage level of the selected bit line; applyingthe word line voltage to a selected memory cell of the memory cellarray, the selected memory cell comprising a first cell transistorconnected to a selected bit line through a first word line transistorand connected to a selected source line; and applying the unselectedsource line voltage to an unselected memory cell of the memory cellarray, the unselected memory cell comprising a second cell transistorconnected to the selected bit line through a second word line transistorand connected to an unselected source line.
 19. The method of claim 18,wherein the generating the word line voltage comprises: adjusting alevel of the word line voltage such that a change in the voltage levelof the selected bit line based on a change in the ambient temperature iswithin a specific range.
 20. The method of claim 18, further comprising:applying a suppression voltage to an unselected bit line; and applying aselected source line voltage to the selected memory cell such that hotcarriers are injected into a floating gate of the selected memory cell.